With the spread of mobile products represented by cell phones, miniaturization of an LSI has been developed in order to further accelerate a processing speed and to further save a power consumption. There is a tendency that the thickness of a gate insulation film of a transistor is further reduced in accordance with the miniaturization of an LSI.
A silicon oxide film (SiO2) has been conventionally used as a gate insulation film of a MOS transistor. However, a silicon oxide film having a thickness of not more than 2 nm has a poor insulation performance, so that a leak current is increased. With increase in the gate leak current, a power consumption is significantly increased. When such a gate insulation film is employed in a mobile product, an available time of a battery in the mobile product is reduced. In addition, because of a thinner gate insulation film, there is a possibility that impurities such as boron are dispersed from a gate electrode into the gate insulation film. This phenomenon impairs the performance and the reliability of the transistor.
In order to cope with this, use of a high dielectric constant film (High-k film) having a dielectric constant higher than that of SiO2 has been considered. A hafnium-based material (HfO2, HfSiOx, and so on) is regarded as a typical promising material. However, the use of a High-k film in a manufacturing process of a semiconductor device has not been long, there is a lot of room for improvement. For example, establishment of technique for selectively removing a High-k film has been expected.
In a manufacturing process of a gate electrode, a High-k film functions as a stopper of an etching. Thus, the High-k film is selectively left in the etching step. Thereafter, the High-k film is required to be selectively peeled and removed. A chemical agent such as hydrofluoric acid (HF), which has been conventionally used for removing a gate insulation film (SiO2), cannot directly remove the annealed High-k film. Thus, there has been proposed that a wet cleaning is performed after a modification process of a plasma processing, so as to remove the High-k film (see, for example, US Patent Publication No. 2003/0230549, and “Selective Wet Etching of Hf-based Layers” by M. Claes, et al. (204th Meetings of The Electrochemical Society) [See, Website of The Electrochemical Society, Inc; http://www.electrochem.org/meetings/past/204/abstracts/symposia/pif1.htm]”)
On the other hand, in a manufacturing process of a gate electrode of a MOS transistor, thicknesses of an anti-reflective coating (ARC) film and a photoresist film, which are used in an etching, are made thinner with a view to miniaturizing the gate electrode. In particular, when an aligner of a high numerical aperture is used, it is more important to make thinner a photoresist film. However, the reduced thickness of the photoresist film may simultaneously make it difficult to accurately etch the film. In order to solve this problem, a hardmask is laid under the photoresist film and the ARC film. Thus, a pattern transfer and a resolution can be improved upon etching. However, in this conventional method of laying a hardmask under the ARC film, an anti-reflective function is not always sufficient, and thus a sufficient resolution and a sufficient lithography process tolerance may not be provided.
Then, there has been proposed an SiC-based film of a multilayer structure having both an anti-reflective function and a hardmask function (see, specification of U.S. Pat. No. 6,316,167, and IEDMTech, dig., p 669, 2003 by K. Babich, et al. (Non-patent Document 1)). With the use of such a film, a significantly excellent anti-reflective function can be obtained, i.e., the reflection in an interface between the film and the photoresist film can be made substantially zero, while allowing the film to exert an appropriate property corresponding to a photoresist and a base film. Further, as compared with the conventional method of laying a hardmask under an ARC film, a resolution and a lithography process tolerance can be remarkably improved.
FIG. 9A to 9H are schematic views showing a part of steps of a conventional gate electrode forming process in which a hardmask is laid under a photoresist film and an ARC film.
FIG. 9A shows a gate layered body which has not been yet etched. On a silicon substrate 201 forming a semiconductor wafer, there is formed a High-k film 202 made of, e.g., HfO2 or HfSiOx, as a gate insulation film. On the High-k film 202, there is formed a polysilicon film 203. On the polysilicon film 203, there are formed a hardmask 204 made of, e.g., silicon dioxide or silicon nitride, and an ARC film 205. On the ARC film 205, there is formed a patterned photoresist film 210.
At first, as shown in FIG. 9B, the ARC film 205 and the hardmask film 204 are etched with the photoresist film 210 used as a mask. Then, as shown in FIG. 9C, the photoresist film 210 is removed. Thereafter, the polysilicon film 203 is etched with the ARC film 205 and the hardmask film 204 used as a mask. As shown in FIG. 9D, due to the etching of the polysilicon film 203, the ARC film 205 is also removed (a film-thickness of the hardmask film 204 is also reduced).
Then, as shown in FIG. 9E, the High-k film 202, which has been exposed by etching the polysilicon film 203, is subjected to a plasma processing. In this step, the High-k film 202 is modified into a porous material mainly by an action of ions contained in the plasma.
After the modification step, as shown in FIG. 9F, an exposed part of the High-k film 202 is peeled and removed by a wet cleaning (wet etching) using a chemical liquid such as HF. Then, as shown in FIG. 9G, a sidewall 207 is formed around the gate layered body. Thereafter, the remaining hardmask 204 is peeled and removed by a combination of the plasma modification process and the wet cleaning. As a result, a gate structure as shown in FIG. 9H can be obtained.
With the above-described series of steps, a gate electrode is formed. In the above conventional art, removal of the High-k film 202 and removal of the hardmask 204 are performed in the steps independent from each other. In other words, the plasma processing and the wet cleaning are repeated twice, respectively. Such an increased number of steps invites problems such as deterioration in a device caused by a plasma damage, side-etching of a gate insulation film in a wet cleaning step, and film-reduction of a buried insulation film.
When a novel material, such as an SiC-based film of a multilayer structure having both an anti-reflective function and a hardmask function, which is shown in the specification of U.S. Pat. No. 6,316,167, and IEDMTech, dig., p 669, 2003 by K. Babich, et al., is used in place of a combination of the ARC and the hardmask, it is necessary to establish a process for efficiently, reliably removing the SiC-based film. However, when a gate electrode is manufactured out of a layered body including an SiC-based film of a multilayer structure and a High-k film as a gate insulation film, the repeated independent removing steps like the conventional process (FIG. 9A to FIG. 9H) may give an adverse effect on a semiconductor device.